1. Field of the Invention
The present invention relates to a method and apparatus for voltage fault protection, and, more particularly, to a method and apparatus for voltage fault protection for an ink jet printhead.
2. Description of the Related Art
It is known for a switching voltage regulator to use some form of fault protection to prevent outputting the wrong voltage, sourcing too much current, and/or over-stressing individual electrical components. However, many forms of fault protection simply shut down the switching voltage regulator while the fault exists. Therefore, if the switching voltage regulator shuts down due to a fault condition, and the fault does not go away, then the switching voltage regulator starts to supply voltage and current again until the fault is redetected. The result is that the switching voltage regulator continues to cycle on and off until the input supply voltage (V13 Bulk) is removed. The buck regulator circuit 10 of FIG. 1, including an over-current protection circuit 11 and a converter 12, illustrates a known fault detection method used on switching voltage regulators in which the above-described problems exist. Over-current protection circuit 11 includes a pulse width modulation controller 13 and an external sense-resistor 14. Regulator 10 is also known as a switch-mode power supply.
In order to provide current-overload protection, external sense-resistor 14 is connected between the input supply voltage (V13 Bulk) of pulse width modulation controller 13 and the drain of a load-carrying field effect transistor (FET) 16. Resistor 14 senses the output current i0 of pulse width modulation controller 10 at node (V13 OUT). The voltage across sense-resistor 14 is fed back to an RSENSE13 VPH pin 18. If RSENSE13 VPH pin 18 reads a voltage exceeding a voltage-trip level, then regulator 10 senses a fault condition and momentarily shuts down the output voltage (V13 OUT) and current of regulator 10 by turning off the cycling of a pulse width modulated signal driving the gate of load-carrying FET 16 on pin 20. By applying no voltage to pin 20 and to the gate of FET 16, pulse width modulation controller 13 turns off FET 16. Regulator 10 re-starts after a fixed time period until the fault condition again causes RSENSE13 VPH pin 18 to exceed a voltage trip level. This current limiting behavior continues, and the output voltage (V13 OUT) drops to an unregulated under voltage condition, until the fault condition is removed. An inductor 22 and a capacitor 24 form a filter to transform a switching (alternating current) voltage on VPH13 SOURCE pin 26 into a direct current voltage at (V13 OUT). The switching voltage on VPH13 SOURCE pin 26 is a pulse width modulated source signal which switches between voltages of V13 Bulk and ground. Diode 28 is a fly-back diode.
What is needed in the art is a voltage and current fault protection circuit for an ink jet printhead that permanently disables the printhead voltage once a fault has been detected.
The present invention provides self-clocking, self-initializing and self-monitoring for over-voltage and under-voltage fault conditions, with a latched fault output signal, for a printhead of an ink jet printer.
The present invention comprises, in one form thereof, an ink jet printhead voltage fault protection apparatus including a power supply and a latching circuit. The latching circuit disables a printhead voltage applied to the printhead by the power supply upon detection of a fault condition associated with the printhead voltage such that the printhead voltage remains disabled until the power supply goes through a power-on reset sequence.
The present invention comprises, in another form thereof, a method of protecting an ink jet printhead from a voltage fault condition and from an over-current fault condition which can cause overheating. The method includes applying a printhead voltage from a power supply to the ink jet printhead. A fault condition associated with the printhead voltage is detected. The printhead voltage is disabled dependent upon the detecting step such that the printhead voltage remains disabled until the power supply is cycled off and then on again.
The latched fault output signal disables the printhead voltage, once a fault has been detected, until the printer goes through a power-on reset sequence. A clocked latch for noise immunity uses a signal derived from a square wave output from the switch-mode power supply for self-clocking and proper shutdown during faults. A self-initializing feature prevents false shutdown during turn-on transients.
The present invention provides an apparatus and method by which an over-voltage and under-voltage fault condition, detected at the output of a switch-mode power supply, results in the permanent disablement of the output. Also, an over-current fault condition is detected when the current limit of the buck regulator results in an under voltage fault condition. This is accomplished by latching the detection of the fault condition until the regulator goes through a power-on reset sequence. The over-voltage and under-voltage protection circuitry is self-clocking by using a switching voltage from the switch-mode power supply to clock in a fault condition to a D-flip-flop, self-initializing through a power-on reset sequence, and self-monitoring during the operation of the switching voltage regulator. The present invention combines the benefits of a clocked latch, for immunity to spurious noise, with a self-clocking feature that is a novel way of disabling the clock for proper latching of fault conditions.
The present invention provides a method by which an over-voltage or under-voltage fault condition, detected on the output of a switch-mode power supply, permanently disables the output by latching the detection of the fault condition until the regulator goes through a power-on reset sequence. The over-voltage and under-voltage protection circuitry is self-clocking by using a switching voltage from the switch-mode power supply to clock-in a fault condition to the D-flip-flop, self-initializing through a power-on reset sequence, and self-monitoring during the operation of the switching voltage regulator. The described method also properly latches off the output of a switching voltage regulator when the over-voltage and under-voltage fault detection circuit is powered-on into a fault condition.
An advantage of the present invention is that the printhead voltage is permanently disabled, instead of cycling on and off, while operating in current limit mode, after a voltage fault has been detected.
Another advantage is that the present invention properly handles power on when a fault condition is present.
Yet another advantage is that voltage transients resulting from turning on the power supply are not interpreted as a voltage fault condition.